Miresga: Achieving High-Performance and Reliable Layer-7 Load Balancing with Programmable Switches

To appear in IEEE Transactions on Computers, 2026

CCF-A THCPL-A

Abstract

As online cloud services continue to scale, ensuring both performance and reliability in layer-7 load balancing has become increasingly critical. Programmable switches offer Tbps-level packet processing with limited flexibility, making them promising yet constrained candidates for accelerating layer-7 load balancing. We present Miresga, a hybrid layer-7 load balancing framework that achieves high performance and reliability through software–hardware co-design. Miresga offloads elephant flows to programmable switches for line-rate forwarding, while front-end servers handle protocol parsing and scheduling, ensuring flexibility. To address the limited memory of the programmable switch, Miresga introduces an eBPF-based back-end agent to manage sequence synchronization. Miresga also employs a distributed RDMA-based state synchronization mechanism for failure tolerance and dynamic traffic migration. Our prototype on a 3.2 Tbps Intel Tofino switch demonstrates up to 3.9× throughput improvement and 60% latency reduction over optimized software baselines, while maintaining stable throughput during front-end server failures and recoveries.

This is the extended journal version of our conference paper published at The Web Conference 2025 (WWW ‘25): Miresga: Accelerating Layer-7 Load Balancing with Programmable Switches. The code repository is shared between both versions: github.com/THUNAME/Miresga.

Kindly noting that this repo is under GNU Affero Public License v3 . Please ensure compliance with the terms of the license when using this repository.